EP1SGX10C Datasheet, PDF (56/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
DPA Operation
The DPA receiver circuitry contains the dynamic phase selector, the
deserializer, the synchronizer, and the data realigner (see Figure 41). This
section describes the DPA operation, synchronization and data
realignment. In the SERDES with DPA mode, the source clock is fed to the
fast PLL through the dedicated clock input pins. This clock is multiplied
by the multiplication value W to match the serial data rate.
For information on the deserializer, see “Principles of SERDES
Operation” on page 47.
Figure 41. DPA Receiver Circuit
DPA Receiver Circuit
dpll_reset
Serial Data (1)
rxin+
rxin-
inclk+
inclk -
Dynamic
Phase
Selector
Deserializer ₁₀
Synchronizer
10
8
×W Clock (1)
Fast PLL
×1 Clock
Parallel
Clock
Note to Figure 41:
(1) These are phase-matched and retimed high-speed clocks and data.
Data
Realigner
Stratix GX Logic Array
GCLK
RCLK
Reset
The dynamic phase selector matches the phase of the high-speed clock
and data before sending them to the deserializer.
The fast PLL supplies eight phases of the same clock (each a separate tap
from a four-stage differential VCO) to all the differential channels
associated with the selected fast PLL. The DPA circuitry inside each
channel locks to a phase closest to the serial data’s phase and sends the
retimed data and the selected clock to the deserializer. The DPA circuitry
automatically performs this operation and is not selected by the designer.
Each channel’s DPA circuit can independently choose a different clock
phase. The data phase detection and the clock phase selection process is
automatic and continuous. The eight phases of the clock give the DPA
circuit a granularity of one eighth of the unit interval (UI) or 125 ps at
1 Gbps. Figure 42 illustrates the clocks generated by the fast PLL circuitry
and their relationship to a data stream.
56
Preliminary
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