EP1SGX10C Datasheet, PDF (220/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 100. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
t_MRAMDATABSU
t_MRAMDATABH
t_MRAMADDRBSU
t_MRAMADDRBH
t_MRAMDATACO1
t_MRAMDATACO2
t_MRAMCLKHL
t_MRAMCLR
Parameter
B port setup time before clock
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Table 101. Routing Delay Internal Timing Microparameter Descriptions
Symbol
t_R4
t_R8
t_R24
t_C4
t_C8
t_C16
t_LOCAL
Parameter
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an R8 line with average loading; covers a distance
of eight LAB columns
Delay for an R24 line with average loading; covers a distance
of 24 LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Delay for an C8 line with average loading; covers a distance
of eight LAB rows
Delay for an C16 line with average loading; covers a distance
of 16 LAB rows
Local interconnect delay
Table 102. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 1 of 2)
Symbol
t_{A N A L O G R E S E T P W}
t_{D I G I T A L R E S E T P W}
t_{T X _ P L L _ L O C K}
Parameter
Pulse width to power down analog circuits.
Pulse width to reset digital circuits
The time it takes the tx_pll to lock to the reference
clock.
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Preliminary
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