EP1SGX10C Datasheet, PDF (126/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
For FIR filters, the DSP block combines the four-multipliers adder mode
with the shift register inputs. One set of shift inputs contains the filter
data, while the other holds the coefficients loaded in serial or parallel. The
input shift register eliminates the need for shift registers external to the
DSP block (i.e., implemented in LEs). This architecture simplifies filter
design since the DSP block implements all of the filter circuitry.
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, DSP blocks can be cascaded with
additional adder stages implemented in LEs.
Table 36 shows the different number of multipliers possible in each DSP
block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions.
Table 36. Multiplier Size & Configurations per DSP block
DSP Block Mode
Multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
9×9
Eight multipliers with
eight product outputs
Two multiply and
accumulate (52 bits)
Four sums of two
multiplier products each
Two sums of four
multiplier products each
18 × 18
36 × 36 (1)
Four multipliers with four One multiplier with one
product outputs
product output
Two multiply and
–
accumulate (52 bits)
Two sums of two
–
multiplier products each
One sum of four multiplier –
products each
Note to Table 36:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned
implementations.
DSP Block Interface
Stratix GX device DSP block outputs can cascade down within the same
DSP block column. Dedicated connections between DSP blocks provide
fast connections between the shift register inputs to cascade the shift
register chains. The designer can cascade DSP blocks for 9 × 9- or 18 × 18-
bit FIR filters larger than four taps, with additional adder stages
implemented in LEs. If the DSP block is configured as 36 × 36 bits, the
adder, subtractor, or accumulator stages are implemented in LEs. Each
DSP block can route the shift register chain out of the block to cascade two
full columns of DSP blocks.
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Preliminary
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