EP1SGX10C Datasheet, PDF (143/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Enhanced PLLs
Stratix GX devices contain up to four enhanced PLLs with advanced
clock management features. Figure 95 shows a diagram of the enhanced
PLL.
Figure 95. Stratix GX Enhanced PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
From Adjacent PLL
Post-Scale
Counters
Programmable
Time Delay on
Each PLL Port
/l0
∆t
CLK0
CLK1
Clock
Switch-Over
Circuitry
Phase Frequency
Detector
Spread
Spectrum
/n
∆t
PFD
Charge
Pump
Loop
Filter
8
VCO
/l1
∆t
4
/g0
∆t
/g1
∆t
(1)
FBIN
∆t
/m
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
/g2
∆t
/g3
∆t
/e0
∆t
/e1
∆t
4
/e2
∆t
/e3
∆t
Regional
Clocks
Global
Clocks
I/O Buffers ₍₂₎
to I/O or general
routing
I/O Buffers (3)
Notes to Figure 95:
(1) External feedback is available in PLLs 5 and 6.
(2) This external output is available from the g0 counter for PLLs 11 and 12.
(3) These counters and external outputs are available in PLLs 5 and 6.
Altera Corporation
143
Preliminary