EP1SGX10C Datasheet, PDF (173/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
Slew-Rate Control
The output buffer for each Stratix GX device I/O pin has a programmable
output slew-rate control that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Each
I/O pin has an individual slew-rate control, allowing the designer to
specify the slew rate on a pin-by-pin basis. The slew-rate control affects
both the rising and falling edges.
Bus Hold
Each Stratix GX device I/O pin provides an optional bus-hold feature.
The bus-hold circuitry can weakly hold the signal on an I/O pin at its last-
driven state. Since the bus-hold feature holds the last-driven state of the
pin until the next input signal is present, an external pull-up or pull-down
resistor is not needed to hold a signal level when the bus is tri-stated.
Table 46 shows bus hold support for different pin types.
Table 46. Bus Hold Support
I/O pins
Pin Type
CLK[15..0]
CLK[0,1,2,3,8,9,10,11]
FCLK
FPLL[7..10]CLK
Bus Hold
v
v
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than V_CCIO to prevent
overdriving signals. If the bus-hold feature is enabled, the programmable
pull-up option cannot be used. Disable the bus-hold feature when using
open-drain outputs with the GTL+ I/O standard or when the I/O pin has
been configured for differential signals.
Altera Corporation
173
Preliminary