EP1SGX10C Datasheet, PDF (69/262 Pages) Altera Corporation – StratixGX FPGA Family

Logic Elements
Figure 50. LE in Dynamic Arithmetic Mode
LAB Carry-In
Carry-In0
Carry-In1
addnsub
(LAB Wide)
(1)
sload
sclear
(LAB Wide) (LAB Wide)
Register chain
connection
aload
(LAB Wide)
data1
data2
data3
LUT
ALD/PRE
ADATA Q
D
LUT
ENA
CLRN
clock (LAB Wide)
LUT
ena (LAB Wide)
aclr (LAB Wide)
LUT
Register Feedback
Carry-Out0 Carry-Out1
Note to Figure 50:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
Altera Corporation
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in arithmetic mode. The carry-select chain uses the redundant carry
calculation to increase the speed of carry functions. The LE is configured
to calculate outputs for a possible carry-in of 1 and carry-in of 0 in
parallel. The carry-in0 and carry-in1 signals from a lower-order bit
feed forward into the higher-order bit via the parallel carry chain and feed
into both the LUT and the next portion of the carry chain. Carry-select
chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel
pre-computation of carry chains. Because the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delay between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Stratix GX
architecture to implement high-speed counters, adders, multipliers,
parity functions, and comparators of arbitrary width.
Figure 51 shows the carry-select circuitry in an LAB for a 10-bit full adder.
One portion of the LUT generates the sum of two bits using the input
signals and the appropriate carry-in bit; the sum is routed to the output
of the LE. The register can be bypassed for simple adders or used for
69
Preliminary