EP1SGX10C Datasheet, PDF (129/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock
Networks
PLLs & Clock Networks
clock signals are routed from LAB row clocks and are generated from
specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in Table 37.
Table 37. DSP Block Signal Sources & Destinations
LAB Row at
Interface
Control Signals
Generated
1
signa
2
aclr0
accum_sload0
3
addnsub1
clock0
ena0
4
aclr1
clock1
ena1
5
aclr2
clock2
ena2
6
sign_b
clock3
ena3
7
clear3
accum_sload1
8
addnsub3
Data Inputs
A1[17..0]
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
Data Outputs
OA[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
OG[17..0]
OH[17..0]
Stratix GX devices provide a hierarchical clock structure and multiple
PLLs with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Stratix GX devices contain up to four enhanced PLLs and up to four fast
PLLs. In addition, there are four receiver PLLs and one transmitter PLL
per transceiver block located on the right side of Stratix GX devices.
Global & Hierarchical Clocking
Stratix GX devices provide 16 dedicated global clock networks,
16 regional clock networks (four per device quadrant), 8 dedicated fast
regional clock networks within EP1SGX10 and EP1SGX25, and 16
dedicated fast regional clock networks within EP1SGX40 devices.
Altera Corporation
129
Preliminary