EP1SGX10C Datasheet, PDF (186/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 57. Stratix GX JTAG Timing Parameters & Values (Part 2 of 2)
Symbol
Parameter
Min (ns) Max (ns)
t_{J P H}
JTAG port hold time
45
t_{J P C O} JTAG port clock to output
25
t_{J P Z X}
JTAG port high impedance to valid output
25
t_{J P X Z}
JTAG port valid output to high impedance
25
t_{J S S U} Capture register setup time
20
t_{J S H}
Capture register hold time
45
t_{J S C O} Update register clock to output
35
t_{J S Z X}
Update register high impedance to valid output
35
t_{J S X Z}
Update register valid output to high impedance
35
f ^{For more information on JTAG, see the following documents:}
■ AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
■ Jam Programming & Test Language Specification
SignalTap
Embedded Logic
Analyzer
Stratix GX devices feature the SignalTap embedded logic analyzer, which
monitors design operation over a period of time through the
IEEE Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at
speed without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix GX architecture are
configured with CMOS SRAM elements. Stratix GX devices are
reconfigurable and are 100% tested prior to shipment. As a result, the
designer does not have to generate test vectors for fault coverage
purposes, and can instead focus on simulation and design verification. In
addition, the designer does not need to manage inventories of different
ASIC designs. Stratix GX devices can be configured on the board for the
specific functionality required.
Stratix GX devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix GX devices via a serial data stream.
Stratix GX devices can be configured in under 100 ms using 8-bit parallel
data at 100 MHz. The Stratix GX device’s optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
186
Preliminary
Altera Corporation