EP1SGX10C Datasheet, PDF (224/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 106. M512 Block Internal Timing Microparameters
Symbol
t_M512RC
t_M512WC
t_M512WERESU
t_M512WERH
t_M512DATASU
t_M512DATAH
t_M512WADDRASU
t_M512WADDRH
t_M512DATACO1
t_M512DATACO2
t_M512CLKHL
t_M512CLR
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
3,340
3,816
4,387 ns
3,318
3,590
4,128 ns
110
123
141
ns
34
38
43
ns
110
123
141
ns
34
38
43
ns
110
123
141
ns
34
38
43
ns
424
472
541
ns
3,366
3,846
4,421 ns
150
167
192
ns
170
189
217
ns
Table 107. M4K Block Internal Timing Microparameters (Part 1 of 2)
Symbol
t_M4KRC
t_M4KWC
t_M4KWERESU
t_M4KWERH
t_M4KDATASU
t_M4KDATAH
t_M4KWADDRASU
t_M4KWADDRH
t_M4KRADDRASU
t_M4KRADDRH
t_M4KDATABSU
t_M4KDATABH
t_M4KADDRBSU
t_M4KADDRBH
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
3,807
4,320
4,967 ns
2,556
2,840
3,265 ns
131
149
171
ns
34
38
43
ns
131
149
171
ns
34
38
43
ns
131
149
171
ns
34
38
43
ns
131
149
171
ns
34
38
43
ns
131
149
171
ns
34
38
43
ns
131
149
171
ns
34
38
43
ns
224
Preliminary
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