EP1SGX10C Datasheet, PDF (184/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 54. Stratix GX JTAG Instructions (Part 2 of 2)
JTAG Instruction
CLAMP (1)
ICR instructions
PULSE_NCONFIG
CONFIG_IO
SignalTap
instructions
Description
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Stratix GX device through the JTAG port with a MasterBlaster^TM
or ByteBlasterMV^TM download cable, or when using a .jam file or .jbc file with an
embedded processor.
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical
pin is unaffected.
Allows the IOE standards to be configured through the JTAG chain. Stops configuration if
executed during configuration. Can be executed before or after configuration.
Monitors internal device operation with the SignalTap embedded logic analyzer.
Note to Table 54:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
The Stratix GX device instruction register length is 10 bits, and the
USERCODE register length is 32 bits. Tables 55 and 56 show the
boundary-scan register length and IDCODE information for Stratix GX
devices.
Table 55. Stratix GX Boundary-Scan Register Length
Device
EP1SGX10
EP1SGX25
EP1SGX40
Boundary-Scan Register Length
1,029
1,665
1,941
Table 56. 32-Bit Stratix GX Device IDCODE (Part 1 of 2)
Device
Version (4 Bits)
EP1SGX10
EP1SGX25
0000
0000
IDCODE (32 Bits) (1)
Part Number (16 Bits)
Manufacturer Identity
(11 Bits)
0010 0000 0100 0001
0010 0000 0100 0011
000 0110 1110
000 0110 1110
LSB (1 Bit) (2)
1
1
184
Preliminary
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