EP1SGX10C Datasheet, PDF (36/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 14. BIST Data Output & Verifier Alignment Pattern (Part 2 of 2)
BIST Mode
Output
Polynomials
PRBS 16-bit
2⁸ – 1
x⁸ + x⁷ + x⁵ + x³ + 1
PRBS 20-bit
2¹⁰ – 1
x¹⁰ + x⁷ + 1
Incremental 10-bit
K28.5, K27.7, Data (00-FF
incremental), K28.0, K28.1,
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7 (1)
Incremental 20-bit
K28.5, K27.7, Data (00-FF
incremental), K28.0, K28.1,
K28.2, K28.3, K28.4, K28.6,
K28.7, K23.7, K30.7, K29.7 (1)
High frequency 1010101010
Low frequency 0011111000
Mixed frequency 0011111010 or 1100000101
Verifier Word Alignment Pattern
1000000011111111
1111111111
0101111100 (K28.5)
0101111100 (K28.5)
Note to Table 14:
(1) This output repeats.
Stratix GX Clocking
The Stratix GX global clock can be driven by certain REFCLKB pins, all
transmitter PLL outputs, and all receiver PLL outputs. The REFCLKB pins
(except for transceiver block 0 and transceiver block 4) can drive inter-
transceiver and global clock lines as well as feed the transmitter and
receiver PLLs. The output of the transmitter PLL can only feed global
clock lines and the reference clock port of the receiver PLL.
Figures 28 and 29 are diagrams of the Inter-Transceiver line connections
as well as the global clock connections for the EP1SGX25F and
EP1SGX40G devices. For devices with fewer transceivers, ignore the
information about the unavailable transceiver blocks.
36
Preliminary
Altera Corporation