EP1SGX10C Datasheet, PDF (131/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 85. Global Clock Resources
CLK[15..12]
CLK[3..0]
Global Clock [15..0]
Transceiver
Clocks
CLK[7..4]
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each
quadrant of the Stratix GX device that are driven by the same dedicated
CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver
clocks. The regional clock networks only pertain to the quadrant they
drive into. The regional clock networks provide the lowest clock delay
and skew for logic contained within a single quadrant. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in Figure 86.
Altera Corporation
131
Preliminary