EP1SGX10C Datasheet, PDF (223/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 104. IOE Internal Timing Microparameters
Symbol
t_SU
t_H
t_CO
t_{PIN2COMBOUT_R}
t_{PIN2COMBOUT_C}
t_{COMBIN2PIN_R}
t_{COMBIN2PIN_C}
t_CLR
t_PRE
t_CLKHL
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
64
68
68
ns
76
80
80
ns
162
171
171 ns
1,038
1,093
1,256 ns
927
976
1,122 ns
2,944
3,099
3,563 ns
3,189
3,357
3,860 ns
262
276
317
ns
262
276
317
ns
90
95
109
ns
Table 105. DSP Block Internal Timing Microparameters
Symbol
t_SU
t_H
t_CO
t_INREG2PIPE18
t_INREG2PIPE9
t_{PIPE2OUTREG2ADD}
t_{PIPE2OUTREG4ADD}
t_PD9
t_PD18
t_PD36
t_CLR
t_CLKHL
-5 Speed
Grade
-6 Speed
Grade
-7 Speed
Grade
Unit
Min Max Min Max Min Max
0
0
0
ns
67
75
86
ns
142
158
181 ns
2,613
2,982
3,429 ns
3,390
3,993
4,591 ns
2,002
2,203
2,533 ns
2,899
3,189
3,667 ns
3,709
4,081
4,692 ns
4,795
5,275
6,065 ns
7,495
8,245
9,481 ns
450
500
575
ns
1,350
1,500
1,724
ns
Altera Corporation
223
Preliminary