EP1SGX10C Datasheet, PDF (116/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 34 shows the summary of input register modes for the DSP block.
Table 34. Input Register Modes
Register Input Mode
Parallel input
Shift register input
9×9
v
v
18 × 18
v
v
36 × 36
v
Multiplier
The multiplier supports 9 × 9-, 18 × 18-, or 36 × 36-bit multiplication. Each
DSP block supports eight possible 9 × 9-bit or smaller multipliers. There
are four multiplier blocks available for multipliers larger than 9 × 9 bits
but smaller than 18 × 18 bits. There is one multiplier block available for
multipliers larger than 18 × 18 bits but smaller than or equal to 36 × 36 bits.
The ability to have several small multipliers is useful in applications such
as video processing. Large multipliers greater than 18 × 18 bits are useful
for applications such as the mantissa multiplication of a single-precision
floating-point number.
The multiplier operands can be signed or unsigned numbers, where the
result is signed if either input is signed as shown in Table 35. The sign_a
and sign_b signals provide dynamic control of each operand’s
representation: a logic 1 indicates the operand is a signed number, a logic
0 indicates the operand is an unsigned number. These sign signals affect
all multipliers and adders within a single DSP block and designers can
register them to match the data path pipeline. The multipliers are full
precision (that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit
multiply, and so on), regardless of whether sign_a or sign_b set the
operands as signed or unsigned numbers.
Table 35. Multiplier Signed Representation
Data A
Unsigned
Unsigned
Signed
Signed
Data B
Unsigned
Signed
Unsigned
Signed
Result
Unsigned
Signed
Signed
Signed
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Preliminary
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