EP1SGX10C Datasheet, PDF (180/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 114. LVDS Input Differential On-Chip Termination
Transmitting
Device
Receiving Device with
Differential Termination
Z₀
+
+
Ð
R_D
Ð
Z₀
I/O banks on the left and right side of the device support LVDS receiver
(far-end) differential termination.
Table 50 shows the Stratix GX device differential termination support.
Table 50. Differential Termination Supported by I/O Banks
Differential Termination Support
Differential termination (1), (2)
I/O Standard Support
LVDS
Top & Bottom
Banks (3, 4, 7 & 8)
Left Banks (1 & 2)
v
Notes to Table 50:
(1) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination.
(2) Differential termination is only supported for LVDS because of a 3.3-V V_{C C I O} .
Table 51 shows the termination support for different pin types.
Table 51. Differential Termination Support Across Pin Types
Pin Type
R_D
Top and bottom I/O banks (3, 4, 7, and 8)
DIFFIO_RX[]
v
CLK[0,2,9,11],CLK[4-7],CLK[12-15]
CLK[1,3,8,10]
v
FCLK
FPLL[7..10]CLK
The differential on-chip resistance at the receiver input buffer is
118 Ω ±20 %.
180
Preliminary
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