EP1SGX10C Datasheet, PDF (12/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Transmitter Path
This section describes the data path through the Stratix GX transmitter
(see Figure 4). Data travels through the Stratix GX transmitter via the
following modules:
■ Transmitter PLL
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel to serial converter)
■ Transmitter output buffer
Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the
reference clock and generates the following signals:
■ High-speed serial clock used by the serializer
■ Slow-speed reference clock used by the receiver
■ Slow-speed clock used by the logic array (divisible by two for
double-width mode)
The INCLK clock is the input into the transmitter PLL. There is one INCLK
clock per transceiver block. This clock can be fed by either the REFCLKB
pin, PLD routing, or the inter-transceiver routing line. See the section
“Stratix GX Clocking” on page 36 for more information about the inter-
transceiver lines.
The transmitter PLL in each transceiver block clocks the circuits in the
transmit path. The transmitter PLL is also used to train the receiver PLL.
If no transmit channels are used in the transceiver block, the transmitter
PLL can be turned off. Figure 5 is a block diagram of the transmitter PLL.
Figure 5. Transmitter PLL Block Diagram Note (1)
÷m
Inter Quad Routing (IQ1)
Inter Quad Routing (IQ2)
Global Clks, IO Bus, Gen Routing
INCLK
PFD
Up
Charge Pump +
Down Loop Filter
VCO
Dedicated
Local
÷2
REFCLKB
Note to Figure 5:
(1) The divider in the PLL divides by 4, 8, 10, 16, or 20.
Clock
Driver
High Speed Clock
Low Speed Clock
12
Preliminary
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