EP1SGX10C Datasheet, PDF (149/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
pair of output pins (four pins total) has dedicated VCC and GND pins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as
well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology,
differential HSTL, and differential SSTL. Table 40 shows which I/O
standards the enhanced PLL clock pins support. When in single-ended or
differential mode, the two outputs operate off the same power supply.
Both outputs use the same standards in single-ended mode to maintain
performance. Designers can also use the external clock output pins as
user output pins if external enhanced PLL clocking is not needed.
Table 40. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5-V HSTL class I
1.5-V HSTL class II
SSTL-18 class I
SSTL-18 class II
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Input
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLLENABLE
v
v
Output
EXTCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
149
Preliminary