EP1SGX10C Datasheet, PDF (258/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 150 describes the Stratix GX device fast PLL specifications.
Table 150. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Symbol
f_IN
f_OUT
f_{OUT_EXT}
f_VCO
t_INDUTY
t_INJITTER
t_DUTY
t_JITTER
t_LOCK
m
l0, l1, g0
t_ARESET
Parameter
Min
CLKIN frequency (for m = 1) (1)
300
CLKIN frequency (for m = 2 to 19)
300/
m
CLKIN frequency (for m = 20 to 32)
10
Output frequency for internal global or 9.4
regional clock (2)
Output frequency for external clock
9.375
VCO operating frequency
300
CLKIN duty cycle
40
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin (3) 45
Period jitter for DIFFIO clock out (3)
Period jitter for internal global or
regional clock
Time required for PLL to acquire lock 10
Multiplication factors for m counter (3) 1
Multiplication factors for l0, l1, and g0
1
counter (4), (5)
Minimum pulse width on areset
10
signal
Max
717
1,000/m
1,000/m
420
717
1,000
60
±200
55
±80
±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk
100
32
32
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
ps
%
ps
ps or
mUI
µs
Integer
Integer
ns
Table 151. Fast PLL Specifications for -7 & -8 Speed Grades (Part 1 of 2)
Symbol
f_IN
f_OUT
f_{OUT_EXT}
f_VCO
t_INDUTY
t_INJITTER
Parameter
Min
CLKIN frequency (for m = 1) (1),
300
CLKIN frequency (for m = 2 to 19)
300/
m
CLKIN frequency (for m = 20 to 32)
10
Output frequency for internal global or 9.375
regional clock (2)
Output frequency for external clock
9.4
VCO operating frequency
300
CLKIN duty cycle
40
Period jitter for CLKIN pin
Max
640
700/m
700/m
420
500
700
60
±200
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
ps
258
Preliminary
Altera Corporation