EP1SGX10C Datasheet, PDF (34/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 25. Data Path in Reverse Serial Loopback Mode
Deserializer
Word
Aligner
Clock
Recovery
Unit
BIST PRBS
Verifier
Channel
Aligner
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
BIST
Incremental
Verifier
Phase
Compensation
FIFO
Serializer
Active Path
Non-active Path
8B/10B
Encoder
BIST PRBS
Generator
Byte
Serializer
Phase
Compensation
FIFO
BIST
Generator
BIST (Built-In Self Test)
The Stratix GX transceiver has built-in self test modes to aid in debug and
testing. The BIST modes are set in the Stratix GX MegaWizard Plug-In
Manager in the Quartus II software. Only one BIST mode can be set for
any single instance of the transceiver block. The BIST mode applies to all
channels used in a transceiver.
The following is a list of the available BIST modes:
■ PRBS generator and verifier
■ Incremental mode generator and verifier
■ High-frequency generator
■ Low-frequency generator
■ Mixed-frequency generator
Figures 26 and 27 are diagrams of the BIST PRBS data path and the BIST
incremental data path, respectively.
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Preliminary
Altera Corporation