EP1SGX10C Datasheet, PDF (154/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
The clkena signals control the enhanced PLL regional and global
outputs. Each regional and global output port has its own clkena signal.
The clkena signals synchronously disable or enable the clock at the PLL
output port by gating the outputs of the g and l counters. The clkena
signals are registered on the falling edge of the counter output clock to
enable or disable the clock without glitches. Figure 100 shows the
waveform example for a PLL clock port enable. The PLL can remain
locked independent of the clkena signals since the loop-related counters
are not affected. This feature is useful for applications that require a low
power or sleep mode. Upon re-enabling, the PLL does not need a
resynchronization or relock period. The clkena signal can also disable
clock outputs if the system is not tolerant to frequency overshoot during
resynchronization.
The extclkena signals work in the same way as the clkena signals, but
they control the external clock output counters (e0, e1, e2, and e3). Upon
re-enabling, the PLL does not need a resynchronization or relock period
unless the PLL is using external feedback mode. In order to lock in
external feedback mode, the external output must drive the board trace
back to the FBIN pin.
Figure 100. extclkena Signals
COUNTER
OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix GX devices contain up to four fast PLLs with high-speed serial
interfacing ability, along with general-purpose features. Figure 101 shows
a diagram of the fast PLL.
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Preliminary
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