EP1SGX10C Datasheet, PDF (134/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 88. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Fast Clock Fast Clock Fast Clock Fast Clock
[3]
[2]
[1]
[0]
fclk[1..0]
[4]
[5]
[6]
[7]
Fast Clock Fast Clock Fast Clock Fast Clock
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, 4 regional clock lines, and 2 fast
regional clock lines. Multiplexers are used with these clocks to form 8-bit
busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See Figure 89.
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Preliminary
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