EP1SGX10C Datasheet, PDF (50/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 36. Stratix GX High-Speed Interface Serialized in ×10 Mode
Stratix GX
Logic Array
Transmitter Circuit
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
×W
Fast
PLL
TXLOADEN
TXOUT+
TXOUT−
Figure 37. Transmitter Timing Diagram
Internal ×1 clock
Internal ×10 clock
TXLOADEN
Receiver
data input
n–1 n–0 9
8
7
6
5
4
3
2
1
0
DPA Block Overview
Each Stratix GX receiver channel features a DPA block. The block contains
a dynamic phase selector for phase detection and selection, a SERDES, a
synchronizer, and a data realigner circuit. Designers can bypass the
dynamic phase aligner without affecting the basic source-synchronous
operation of the channel by using a separate deserializer shown in
Figure 38.
50
Preliminary
Altera Corporation