EP1SGX10C Datasheet, PDF (9/262 Pages) Altera Corporation – StratixGX FPGA Family

Figure 3. Stratix GX Transceiver Block
PLD
Logic
Array
Receiver Channel 0
Channel 0
Transmitter Channel 0
Transceiver Blocks
Receiver Pins
Transmitter Pins
PLD
Logic
Array
PLD
Logic
Array
Receiver Channel 1
Channel 1
Transmitter Channel 1
XAUI
Receiver
State
Machine
XAUI
Transmitter
State
Machine
Channel
Aligner
State
Machine
Transmitter
PLL
Receiver Pins
Transmitter Pins
PLD
Logic
Array
PLD
Logic
Array
PLD
Logic
Array
Receiver Channel 2
Channel 2
Transmitter Channel 2
Receiver Channel 3
Channel 3
Transmitter Channel 3
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Altera Corporation
9
Preliminary