EP1SGX10C Datasheet, PDF (212/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 88. 1.5-V HSTL Class I Specifications (Part 2 of 2)
Symbol
V_OH
V_OL
Parameter
High-level output voltage
Low-level output voltage
Conditions Minimum
I_{O H} = 8 mA (1) V_{C C I O} – 0.4
I_{O H} = –8 mA (1)
Typical Maximum
0.4
Units
V
V
Table 89. 1.5-V HSTL Class II Specifications
Symbol
V_CCIO
V_REF
V_TT
V_IH (DC)
V_IL (DC)
V_IH (AC)
V_IL (AC)
V_OH
V_OL
Parameter
Conditions Minimum Typical
Output supply voltage
1.4
1.5
Input reference voltage
0.68
0.75
Termination voltage
0.7
0.75
DC high-level input voltage
DC low-level input voltage
V_{R E F} + 0.1
–0.3
AC high-level input voltage
AC low-level input voltage
V_{R E F} + 0.2
High-level output voltage
Low-level output voltage
I_OH = 16 mA (1) V_{C C I O} – 0.4
I_{O H} = –16 mA (1)
Maximum
1.6
0.9
0.8
V_{R E F} – 0.1
V_{R E F} – 0.2
0.4
Units
V
V
V
V
V
V
V
V
V
Table 90. 1.5-V Differential HSTL Specifications
Symbol
V_CCIO
V_DIF (DC)
V_CM (DC)
V_DIF (AC)
Parameter
I/O supply voltage
DC input differential
voltage
DC common mode input
voltage
AC differential input
voltage
Conditions
Minimum
1.4
0.2
Typical
1.5
Maximum
1.6
0.68
0.9
0.4
Units
V
V
V
V
Table 91. CTT I/O Specifications (Part 1 of 2)
Symbol
V_CCIO
V_{T T} /V_REF
V_IH
V_IL
Parameter
Output supply voltage
Termination and input
reference voltage
High-level input voltage
Low-level input voltage
Conditions
Minimum
3.0
1.35
Typical
3.3
1.5
Maximum
3.6
1.65
V_{R E F} + 0.2
V_{R E F} – 0.2
Units
V
V
V
V
212
Preliminary
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