EP1SGX10C Datasheet, PDF (24/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 11. Possible Combinations of rx_lockedtorefclk & rx_locktodata
rx_locktodata
0
0
1
rx_lockedtorefclk
0
1
x
VCO (lock to mode)
Auto
Reference CLK
DATA
Deserializer (Serial-to-Parallel Converter)
The deserializer converts the serial stream into a parallel 8- or 10-bit data
bus. The deserializer receives the least significant bit first. Figure 16 is a
diagram of the deserializer.
Figure 16. Deserializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
10
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
High-speed
serial clock
Low-speed
parallel clock
Word Aligner
The word aligner aligns the incoming data based on the specific byte
boundaries. The word aligner has three customizable modes of operation:
bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available
for the basic and SONET modes. The word aligner also has two
non-customizable modes of operation, which are the XAUI and GigE
modes.
24
Preliminary
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