EP1SGX10C Datasheet, PDF (40/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 31. EP1SGX25 Receiver PLL Recovered Clock to Fast Regional Clock
Connection
PLD
FCLK[1..0]
Stratix GX
Transceiver Blocks
Block 0
Block 1
Block 2
FCLK[1..0]
Block 3
In the EP1SGX40 device, the receiver PLL recovered clocks from
transceivers 0 and 1 drive RCLK[1..0] while transceivers 2, 3, and 4
drive RCLK[7..6]. The regional clocks feed logic in their associated
regions.
40
Preliminary
Altera Corporation