EP1SGX10C Datasheet, PDF (29/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
Figure 21. Before & After the Channel Aligner
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Rate Matcher
The rate matcher, which is available only in XAUI and GigE modes,
consists of a 12-word deep FIFO buffer and a FIFO controller. The rate
matcher is bypassed when the device is not in XAUI or GigE mode.
In a multi-crystal environment, the rate matcher compensates for up to a
100-ppm difference between the source and receiver clocks.
GigE Mode
In the GigE mode, the rate matcher adheres to the specifications in
clause 36 of the IEEE 802.3 documentation, for idle additions or removals.
The rate matcher performs clock compensation only on /I2/ ordered
sets, composing a /K28.5/+ followed by a /D16.2/-. The rate matcher
does not perform a clock compensation on any other ordered set
combinations. An /I2/ is added or deleted automatically based on the
number of words in the FIFO buffer. A 9’h19C is given at the control and
data ports when the FIFO is in an overflow or underflow condition.
Altera Corporation
29
Preliminary