EP1SGX10C Datasheet, PDF (179/262 Pages) Altera Corporation – StratixGX FPGA Family

I/O Structure
Table 49. I/O Support by Bank (Part 2 of 2)
I/O Standard
SSTL-3 class II
AGP (1× and 2×)
CTT
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
Left Banks
(1 & 2)
v
v
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
v
v
v
Each I/O bank has its own VCCIO pins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard
independently. Each bank also has dedicated VREF pins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same V_CCIO for
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when V_CCIO is 3.3 V, a bank can support
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix GX devices provide differential on-chip termination (LVDS I/O
standard) to reduce reflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix GX devices support internal differential termination with a
nominal resistance value of 137.5 Ω for LVDS input receiver buffers.
LVPECL signals require an external termination resistor. Figure 114
shows the device with differential termination.
Altera Corporation
179
Preliminary