EP1SGX10C Datasheet, PDF (225/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 107. M4K Block Internal Timing Microparameters (Part 2 of 2)
Symbol
t_M4KDATACO1
t_M4KDATACO2
t_M4KCLKHL
t_M4KCLR
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
571
635
729 ns
3,984
4,507
5,182 ns
150
167
192
ns
170
189
255
ns
Table 108. M-RAM Block Internal Timing Microparameters
Symbol
t_MRAMRC
t_MRAMWC
t_MRAMWERESU
t_MRAMWERH
t_MRAMDATASU
t_MRAMDATAH
t_MRAMWADDRASU
t_MRAMWADDRH
t_MRAMRADDRASU
t_MRAMRADDRH
t_MRAMDATABSU
t_MRAMDATABH
t_MRAMADDRBSU
t_MRAMADDRBH
t_MRAMDATACO1
t_MRAMDATACO2
t_MRAMCLKHL
t_MRAMCLR
-5
Min Max
4,364
3,654
25
18
25
18
25
18
25
18
25
18
25
18
1,038
4,362
270
135
-6
Min Max
4,838
4,127
25
20
25
20
25
20
25
20
25
20
25
20
1,053
4,939
300
150
-7
Unit
Min Max
5,562 ns
4,746 ns
28
ns
23
ns
28
ns
23
ns
28
ns
23
ns
28
ns
23
ns
28
ns
23
ns
28
ns
23
ns
1,210 ns
5,678 ns
345
ns
172
ns
Altera Corporation
225
Preliminary