EP1SGX10C Datasheet, PDF (52/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 18. Source-Synchronous Circuitry With & Without DPA (Part 2 of 2)
Feature
Interface pins
Receiver pins
Source-Synchronous Circuitry
Without DPA
With DPA
I/O banks 1 and 2
Dedicated inputs
I/O banks 1 and 2
Dedicated inputs
DPA Input Support
Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to
support differential I/O standards at speeds up to 1 Gbps with DPA (or
up to 840 Mbps without DPA). Stratix GX device source-synchronous
circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each
with a supply voltage of 3.3 V. Refer to the High-Speed Differential I/O
Interfaces in Stratix Devices chapter of the Stratix Handbook, Volume 2 for
more information on these I/O standards. Transmitter pins can be either
input or output pins for single-ended I/O standards. Refer to Table 19.
Table 19. Bank 1 & 2 Input Pins
Input Pin Type
Differential
Single ended
I/O Standard
Differential
Single ended
Receiver Pin
Input only
Input only
Transmitter Pin
Output only
Input or output
Interface & Fast PLL
This section describes the number of channels that support DPA and their
relationship with the PLL in Stratix GX devices. EP1SGX10 and
EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices
have four dedicated fast PLLs for clock multiplication. Table 20 shows the
maximum number of channels in each Stratix GX device that support
DPA.
Table 20. Stratix GX Source-Synchronous Differential I/O Resources (Part 1 of 2)
Device
EP1SGX10C
EP1SGX10D
EP1SGX25C
Fast PLLs
2 (3)
2 (3)
2
Pin Count
672
672
672
Receiver
Channels
(1)
Transmitter
Channels
(1)
22
22
22
22
39
39
Receiver &
Transmitter
Channel Speed
(Gbps) (2)
1
1
1
LEs
10,570
10,570
25,660
52
Preliminary
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