EP1SGX10C Datasheet, PDF (71/262 Pages) Altera Corporation – StratixGX FPGA Family

Logic Elements
Figure 51. Carry Select Chain
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
01
LE1
Sum1
LE2
Sum2
LE3
Sum3
LE4
Sum4
LE5
Sum5
01
A6
B6
LE6
Sum6
A7
LE7
Sum7
B7
A8
LE8
Sum8
B8
A9
LE9
Sum9
B9
A10
LE10 ^Sum10
B10
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
LUT
Sum
LUT
LUT
LUT
Carry-Out0 Carry-Out1
LAB Carry-Out
Altera Corporation
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a
NOT-gate push-back technique. Stratix GX devices support simultaneous
preset/ asynchronous load, and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one preset signal.
In addition to the clear and preset ports, Stratix GX devices provide a
chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
71
Preliminary