EP1SGX10C Datasheet, PDF (235/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Table 130. EP1SGX40 Row Pin Global Clock External I/O Timing Parameters (Part 2 of 2)
Symbol
t_OUTCO
t_INSUPLL
t_INHPLL
t_OUTCOPLL
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Unit
Min
Max
2.000
5.365
2.000
5.775
2.000
6.621
ns
1.126
1.186
1.352
ns
0.000
0.000
0.000
ns
0.500
2.304
0.500
2.427
0.500
2.765
ns
External I/O Delay Parameters
External I/O delay timing parameters, both for I/O standard input and
output adders and programmable input and output delays, are specified
by speed grade, independent of device density.
Tables 131 through 136 show the adder delays associated with column
and row I/O pins. If an I/O standard is selected other than LVTTL 24 mA
with a fast slew rate, add the selected delay to the external t_CO and t_SU I/O
parameters.
Table 131. Stratix GX I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
I/O Standard
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 class I
SSTL-3 class II
-5 Speed Grade
Min
Max
0
0
30
150
210
220
220
0
0
0
0
0
120
–30
–30
-6 Speed Grade
Min
Max
0
0
31
157
220
231
231
0
0
0
0
0
126
–32
–32
-7 Speed Grade
Unit
Min
Max
0
ps
0
ps
35
ps
180
ps
252
ps
265
ps
265
ps
0
ps
0
ps
0
ps
0
ps
0
ps
144
ps
–37
ps
–37
ps
Altera Corporation
235
Preliminary