EP1SGX10C Datasheet, PDF (124/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Designers can use the two-multipliers adder mode for complex
multiplications, which are written as:
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j × [(a × d) + (b × c)]
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a × c) – (b × d)] using one subtractor and the imaginary part
[(a × d) + (b × c)] using one adder, for data widths up to 18 bits. Two
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks. Figure 81 shows an 18-bit
two-multipliers adder.
Figure 81. Two-Multipliers Adder Mode Implementing Complex Multiply
18
18
A
18
18
18
C
18
B
18
18
D
18
A
18
D
18
B
18
C
DSP Block
36
37
Subtractor
36
(A × C) − (B × D)
(Real Part)
36
Adder
37
(A × D) + (B × C)
(Imaginary Part)
36
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18 × 18-bit
multipliers or two different sums of two sets of four 9 × 9-bit multipliers
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications. Figure 82 shows the four multipliers
adder mode.
124
Preliminary
Altera Corporation