EP1SGX10C Datasheet, PDF (43/262 Pages) Altera Corporation – StratixGX FPGA Family

Other Transceiver Features
Table 15. Possible Clocking Connections for Transceivers (Part 2 of 2)
Source
IQ lines
Transmitter
PLL
v (2)
Receiver
PLL
v (2)
Destination
GCLK
RCLK
FCLK
IQ Lines
Notes to Table 15:
(1) REFCLKB from transceiver block 0 and transceiver block 4 does not drive the inter-transceiver lines or the GCLK
lines.
(2) Inter-transceiver line 0 and inter-transceiver line 1 drive the transmitter PLL, while inter-transceiver line 2 drives
the receiver PLLs.
Other
Transceiver
Features
Other important features of the Stratix GX transceivers are the power
down and reset capabilities, the external voltage reference and bias
circuitry, and hot swapping.
Individual Power-Down & Reset for the Transmitter & Receiver
Stratix GX transceivers offer a power saving advantage with their ability
to shut off functions that are not needed. The device can individually
reset the receiver and transmitter blocks and the PLLs. The Stratix GX
device can either globally power down and reset the transmitter and
receiver channels or do each channel separately. Table 16 shows the
connectivity between the reset signals and the Stratix GX logical blocks.
Altera Corporation
43
Preliminary