EP1SGX10C Datasheet, PDF (141/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 93. Global & Regional Clock Connections From Side Pins & Fast PLL Outputs Note (1)
FPLL7CLK
l0
PLL 7 l1
g0
RCLK1
RCLK0
G1 G3
G0 G2
CLK0
CLK1
CLK2
CLK3
l0
PLL 1 l1
g0
l 02
PLL 2 l1
g0
FPLL8CLK
l0
PLL 8 l1
g0
RCLK2
RCLK3
Regional
Clocks
Note to Figure 93:
(1) PLLs 1,2 7, and 8 are fast PLLs. PLLs 7 and 8 do not drive global clocks.
Global
Clocks
Figure 94 shows the global and regional clocking from enhanced PLL
outputs and top CLK pins.
Altera Corporation
141
Preliminary