EP1SGX10C Datasheet, PDF (62/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 45. Stratix GX LAB Structure
Row Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect from
adjacent block
Local Interconnect LAB
Direct link
interconnect to
adjacent block
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
M4K RAM blocks, or DSP blocks from the left and right can also drive an
LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 30 other LEs through fast local and direct link interconnects.
Figure 46 shows the direct link connection.
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Preliminary
Altera Corporation