EP1SGX10C Datasheet, PDF (217/262 Pages) Altera Corporation – StratixGX FPGA Family

Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 95 through 101 describe the
Stratix GX device internal timing microparameters for LEs, IOEs,
TriMatrix memory structures, DSP blocks, and MultiTrack
interconnects.
Table 95. LE Internal Timing Microparameter Descriptions
Symbol
t_SU
t_H
t_CO
t_LUT
t_CLR
t_PRE
t_CLKHL
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinational LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Table 96. IOE Internal Timing Microparameter Descriptions
Symbol
t_SU
t_H
t_CO
t_{PIN2COMBOUT_R}
t_{PIN2COMBOUT_C}
t_{COMBIN2PIN_R}
t_{COMBIN2PIN_C}
t_CLR
t_PRE
t_CLKHL
Parameter
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinational output
Column input pin to IOE combinational output
Row IOE data input to combinational output pin
Column IOE data input to combinational output pin
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Altera Corporation
217
Preliminary