EP1SGX10C Datasheet, PDF (93/262 Pages) Altera Corporation – StratixGX FPGA Family

TriMatrix Memory
Table 31. M-RAM Combined Byte Selection for ×144 Mode Notes (1), (2)
byteena[15..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
[8] = 1
[9] = 1
[10] = 1
[11] = 1
[12] = 1
[13] = 1
[14] = 1
[15] = 1
datain ×144
[8..0]
[17..9]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[80..72]
[89..81]
[98..90]
[107..99]
[116..108]
[125..117]
[134..126]
[143..135]
Notes to Tables 30 and 31:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16, ×32,
×64, and ×128 modes.
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. All input registers—renwe, datain, address,
and byte enable registers—are clocked together from either of the two
clocks feeding the block. The output register can be bypassed. The eight
labclk signals or local interconnect can drive the control signals for the
A and B ports of the M-RAM block. LEs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure 62.
Altera Corporation
93
Preliminary