EP1SGX10C Datasheet, PDF (153/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their
outputs. Designers can use these signals to control PLL resynchronization
and gate PLL output clocks for low-power applications.
The pllenable pin is a dedicated pin that enables/disables PLLs. When
the pllenable pin is low, the clock output ports are driven by GND and
all the PLLs go out of lock. When the pllenable pin goes high again, the
PLLs relock and resynchronize to the input clocks. Designers can choose
which PLLs are controlled by the pllenable signal by connecting the
pllenable input port of the altpll megafunction to the common
pllenable input pin.
The areset signals are reset/resynchronization inputs for each PLL. The
areset signal should be asserted every time the PLL loses lock to
guarantee correct phase relationship between the PLL output clocks.
Users should include the areset signal in designs if any of the following
conditions are true:
■ PLL Reconfiguration or Clock switchover enables in the design.
■ Phase relationships between output clocks need to be maintained
after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input
signals. When driven high, the PLL counters resets, clearing the PLL
output and placing the PLL out of lock. The VCO sets back to its nominal
setting (~700 MHz). When driven low again, the PLL resynchronizes to
its input as it relocks. If the target VCO frequency is below this nominal
frequency, then the output frequency starts at a higher value than desired
as the PLL locks. If the system cannot tolerate this, the clkena signal can
disable the output clocks until the PLL locks.
The pfdena signals control the phase frequency detector (PFD) output
with a programmable gate. If designers disable the PFD, the VCO will
operate at its last set value of control voltage and frequency with some
long-term drift to a lower frequency. The system will continue running
when the PLL goes out of lock or the input clock is disabled. By
maintaining the last locked frequency, the system has time to store its
current settings before shutting down. Designers can either use their own
control signal or a clkloss status signal to trigger pfdena.
Altera Corporation
153
Preliminary