EP1SGX10C Datasheet, PDF (82/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
generate the RAM WREN signal while ensuring its data and address
signals meet setup and hold time specifications relative to the WREN
signal. The output registers can be bypassed. Flow-through reading is
possible in the simple dual-port mode of M512 and M4K RAM blocks by
clocking the read enable and read address registers on the negative clock
edge and bypassing the output registers.
Two single-port memory blocks can be implemented in a single M4K
block as long as each of the two independent block sizes is equal to or less
than half of the M4K block size.
The Quartus II software automatically implements larger memory by
combining multiple TriMatrix memory blocks. For example, two
256 × 16-bit RAM blocks can be combined to form a 256 × 32-bit RAM
block. Memory performance does not degrade for memory blocks using
the maximum number of words available in one memory block. Logical
memory blocks using less than the maximum number of words use
physical blocks in parallel, eliminating any external control logic that
would increase delays. To create a larger high-speed memory block, the
Quartus II software automatically combines memory blocks with LE
control logic.
Parity Bit Support
The memory blocks support a parity bit for each byte. The parity bit,
along with internal LE logic, can implement parity checking for error
detection to ensure data integrity. Designers can also use parity-size data
words to store user-specified control bits. In the M4K and M-RAM blocks,
byte enables are also available for data input masking during write
operations.
Shift Register Support
The designer can configure embedded memory blocks to implement shift
registers for DSP applications such as pseudo-random number
generators, multi-channel filtering, auto-correlation, and cross-
correlation functions. These and other DSP applications require local data
storage, traditionally implemented with standard flip-flops, which can
quickly consume many logic cells and routing resources for large shift
registers. A more efficient alternative is to use embedded memory as a
shift register block, which saves logic cell and routing resources and
provides a more efficient implementation with the dedicated circuitry.
The size of a w × m × n shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n). The size
of a w × m × n shift register must be less than or equal to the maximum
number of memory bits in the respective block: 576 bits for the M512
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Preliminary
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