EP1SGX10C Datasheet, PDF (252/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Table 146. High-Speed I/O Specifications (Part 3 of 4) Notes (1), (2)
Symbol
Conditions
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
DPA Lock Time
Stan-
dard
Train
-ing
Pat-
tern
Trans
-ition
Den-
sity
SPI- 0000 10% 256
256
4, 0000
CSIX 0011
1111
1111
256
Number
of
repet-
itions
Rapid 0000 25% 256
256
IO 1111
256
Number
of
repet-
itions
1001 50% 256
256
0000
256
Number
of
repet-
itions
Misc 1010 100% 256
256
1010
256
Number
of
repet-
itions
0101
256
256
0101
256
Number
of
repet-
itions
TCCS
All
200
200
300 ps
SW
PCML (J = 4, 7, 8, 750
750
800
ps
10)
PCML (J = 2)
900
900
1,200
ps
PCML (J = 1)
1,50
1,500
1,700
ps
0
LVDS and LVPECL 500
500
550
ps
(J = 1)
LVDS, LVPECL,
440
440
500
ps
HyperTransport
technology (J = 2
through 10)
Input jitter
All
tolerance
(peak-to-peak)
250
250
250 ps
252
Preliminary
Altera Corporation