EP1SGX10C Datasheet, PDF (47/262 Pages) Altera Corporation – StratixGX FPGA Family

Source-Synchronous Signaling with DPA
Stratix GX I/O Banks
Stratix GX devices contain 17 I/O banks, as shown in Figure 1 on page 5.
I/O banks one and two support high-speed LVDS, LVPECL, and 3.3-V
PCML inputs and outputs. These two banks also incorporate an
embedded dynamic phase aligner within the source-synchronous
interface (see Figure 41 on page 56). The dynamic phase aligner corrects
for the phase difference between the clock and data lines caused by skew.
The dynamic phase aligner operates automatically and continuously
without requiring a fixed training pattern, and allows the
source-synchronous circuitry to capture data correctly regardless of the
channel-to-clock skew.
Principles of SERDES Operation
Stratix GX devices support source-synchronous differential signaling up
to 1 Gbps in DPA mode, and up to 840 Mbps in non-DPA mode. Serial
data is transmitted and received along with a low-frequency clock. The
PLL can multiply the incoming low-frequency clock by a factor of 1 to 10.
The SERDES factor J can be 8 or 10 for the DPA mode, or 4, 7, 8, or 10 for
all other modes. The SERDES factor does not have to equal the clock
multiplication value. The ×1 and ×2 operation is also possible by
bypassing the SERDES. The SERDES DPA cannot support ×1, ×2, or ×4
natively.
On the receiver side, the high-frequency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the low-
frequency clock. On the transmitter side, the parallel data from the logic
array is first clocked into a parallel-in, serial-out shift register
synchronized with the low-frequency clock and then transmitted out by
the output buffers.
There are two dedicated fast PLLs each in EP1SGX10 to EP1SGX25
devices, and four in EP1SGX40 devices. These PLLs are used for the
SERDES operations as well as general-purpose use.
Stratix GX Differential I/O Receiver Operation (Non-DPA Mode)
Designers can configure any of the Stratix GX source synchronous
differential input channels as a receiver channel (see Figure 34). The
differential receiver deserializes the incoming high-speed data. The input
shift register continuously clocks the incoming data on the negative
transition of the high-frequency clock generated by the PLL clock (×W).
Altera Corporation
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Preliminary