EP1SGX10C Datasheet, PDF (86/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 58. M512 RAM Block Control Signals
Dedicated
8
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
inclocken
outclocken
wren
outclr
inclock
outclock
rden
inclr
86
Preliminary
Altera Corporation