EP1SGX10C Datasheet, PDF (147/262 Pages) Altera Corporation – StratixGX FPGA Family

PLLs & Clock Networks
Figure 97. Dynamically Programmable Counters & Delays in Stratix GX Device Enhanced PLLs
Counters and Clock
Delay Settings are
Programmable
All Output Counters and
Clock Delay Settings can
be Programmed Dynamically
f_REF
÷n
∆t
scandata
scanclk
scanaclr
PFD
Charge
Pump
Loop
Filter
VCO
÷m
∆t
÷g
∆t
÷l
∆t
÷e
∆t
Altera Corporation
PLL reconfiguration data is shifted into serial registers from the logic
array or external devices. The PLL input shift data uses a reference input
shift clock. Once the last bit of the serial chain is clocked in, the register
chain is synchronously loaded into the PLL configuration bits. The shift
circuitry also provides an asynchronous clear for the serial registers.
Programmable Bandwidth
The designer has advanced control of the PLL bandwidth using the
programmable control of the PLL loop characteristics, including loop
filter and charge pump. The PLL’s bandwidth is a measure of its ability to
track the input clock and jitter. A high-bandwidth PLL can quickly lock
onto a reference clock and react to any changes in the clock. It also will
allow a wide band of input jitter spectrum to pass to the output. A low-
bandwidth PLL will take longer to lock, but it will attenuate all high-
frequency jitter components. The Quartus II software can adjust PLL
characteristics to achieve the desired bandwidth. The programmable
bandwidth is tuned by varying the charge pump current, loop filter
resistor value, high frequency capacitor value, and m counter value.
Designers can manually adjust these values if desired. Bandwidth is
programmable from 150 kHz to 2 MHz.
147
Preliminary