EP1SGX10C Datasheet, PDF (44/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Power-down functions are static, in other words., they are implemented
upon device configuration and programmed, through the Quartus II
software, to static values. Resets can be static as well as dynamic inputs
coming from the logic array or pins.
Table 16. Reset Signal Map to Stratix GX Blocks
Reset Signal
rxdigitalreset
vvvvv
vv
rxanalogreset
v
v
v
txdigitalreset v v
v
v
pll_areset
vvvvvvvvvvvvvvvvvv
pllenable
vvvvvvvvvvvvvvvvvv
Voltage Reference Capabilities
Stratix GX transceivers provide voltage reference and bias circuitry. To
set-up internal bias for controlling the transmitter output drivers’ voltage
swing—as well as to provide voltage/current biasing for other analog
circuitry—the internal bandgap voltage reference at 0.7 V is used. To
provide bias for internal pull-up PMOS resistors for I/O termination at
the serial interface of receiver and transmitter channels (independent of
power supply drift, process changes, or temperature variation) an
external resistor, which is connected to the external low voltage power
44
Preliminary
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