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EP1SGX10C Datasheet, PDF (80/262 Pages) Altera Corporation – StratixGX FPGA Family | |||
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Stratix GX FPGA Family
Table 23. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block M4K RAM Block M-RAM Block
(32 Ã 18 Bits) (128 Ã 36 Bits) (4K Ã 144 Bits)
Configurations
512 Ã1
256 Ã 2
128 Ã 4
64 Ã 8
64 Ã 9
32 Ã 16
32 Ã 18
4K Ã 1
2K Ã 2
1K Ã 4
512 Ã 8
512 Ã 9
256 Ã 16
256 Ã 18
128 Ã 32
128 Ã 36
64K Ã 8
64K Ã 9
32K Ã 16
32K Ã 18
16K Ã 32
16K Ã 36
8K Ã 64
8K Ã 72
4K Ã 128
4K Ã 144
Notes to Table 23:
(1) See Table 4â36 for maximum performance information.
(2) The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix GX device must write to the dual-port memory once and then disable the
write-enable ports afterwards.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 55 shows true dual-port memory.
Figure 55. True Dual-Port Memory Configuration
A
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
B
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
80
Preliminary
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
occurs or just read the donât care bits. Single-port memory supports
Altera Corporation
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