EP1SGX10C Datasheet, PDF (244/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
The scaling factors for output pin timing in Table 139 are shown in units
of time per pF unit of capacitance (ps/pF). Add this delay to the
combinational timing path for output or bidirectional pins in addition to
the “I/O Adder” delays shown in Tables 131 through 136 and the “IOE
Programmable Delays” in Tables 137 and 138.
Table 139. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers
LVTTL/LVCMOS Standards
Conditions
Parameter
Value
Drive Strength
24 mA
16 mA
12 mA
8 mA
4 mA
2 mA
Output Pin Adder Delay (ps/pF)
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL
15
–
–
-
25
18
–
–
30
25
25
–
50
35
40
35
60
–
–
80
–
75
120
160
SSTL/HSTL Standards
LVCMOS
8
–
15
20
30
60
Conditions
Class I
Class II
Output Pin Adder Delay (ps/pF)
SSTL-3
SSTL-2
SSTL-1.8 1.5-V HSTL
25
25
25
25
25
20
25
20
GTL+/GTL/CTT/PCI Standards
1.8-V HSTL
25
20
Conditions
Output Pin Adder Delay (ps/pF)
Parameter
Value
GTL+
GTL
CTT
PCI
AGP
V_{C C I O} voltage
3.3 V
18
18
25
20
20
level
2.5 V
15
18
-
-
-
244
Preliminary
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