EP1SGX10C Datasheet, PDF (158/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Figure 102. Stratix GX IOE Structure
Logic Array
OE
OE Register
DQ
OE Register
DQ
Output A
Output Register
DQ
CLK
Output Register
Output B
DQ
Input A
Input B
Input Register
DQ
Input Register
DQ
Input Latch
DQ
ENA
The IOEs are located in I/O blocks around the periphery of the Stratix GX
device. There are up to four IOEs per row I/O block and six IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 103 shows how a row I/O block connects to the logic array.
Figure 104 shows how a column I/O block connects to the logic array.
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Preliminary
Altera Corporation