EP1SGX10C Datasheet, PDF (114/262 Pages) Altera Corporation – StratixGX FPGA Family

Stratix GX FPGA Family
Input Registers
A bank of optional input registers is located at the input of each multiplier
and multiplicand inputs to the multiplier. When these registers are
configured for parallel data inputs, they are driven by regular routing
resources. Designers can use a clock signal, asynchronous clear signal,
and a clock enable signal to independently control each set of A and B
inputs for each multiplier in the DSP block. Designers select these control
signals from a set of four different clock[3..0], aclr[3..0], and
ena[3..0] signals that drive the entire DSP block.
Designers can also configure the input registers for a shift register
application. In this case, the input registers feed the multiplier and drive
two dedicated shift output lines: shiftoutA and shiftoutB. The shift
outputs of one multiplier block directly feed the adjacent multiplier block
in the same DSP block (or the next DSP block) as shown in Figure 76, to
form a shift register chain. This chain can terminate in any block, i.e.,
designers can create any length of shift register chain up to 224 registers.
The designer can use the input shift registers for FIR filter applications.
One set of shift inputs can provide data for a filter, and the other are
coefficients that are optionally loaded in serial or parallel. When
implementing 9 × 9- and 18 × 18-bit multipliers, the designer does not
need to implement external shift registers in LAB LEs. The designer
implements all the filter circuitry within the DSP block and its routing
resources, saving LE and general routing resources for general logic.
External registers are needed for shift register inputs when using
36 × 36-bit multipliers.
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Preliminary
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