EP1SGX10C Datasheet, PDF (39/262 Pages) Altera Corporation – StratixGX FPGA Family

Transceiver Blocks
The receiver PLL can also drive the fast regional, regional clocks, and
local routing adjacent to the associated transceiver block. Figures 30
through 33 show which fast regional and regional clock resource can be
used by the recovered clock.
In the EP1SGX25 device, the receiver PLL recovered clocks from
transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2
and 3 drive RCLK[7..6]. The regional clocks feed logic in their
associated regions.
Figure 30. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock
Connection
Stratix GX
PLD
Transceiver Blocks
Block 0
RCLK[11..10]
Block 1
Block 2
RCLK[9..8]
Block 3
In addition, the receiver PLL’s recovered clocks can drive fast regional
lines (FCLK) as shown Figure 31. The fast regional clocks can feed logic in
their associated regions.
Altera Corporation
39
Preliminary